The present invention relates generally to input and output data transmission, and more particularly, to methods and systems for deterministically transferring data between a processor core clock domain and an input/output clock domain.
Automatic test equipment (ATE) usage is a very important tool for validating semiconductor circuit designs, circuit debug, and testing instruction set based functionality of processors. The current generation of ATE typically require cycle accuracy of data vectors and related determinism of device output signals to strobe for comparison with expected data.
The speed or timing dependent semiconductor defects can be determined using structural delay tests. Unfortunately, there are shortfalls in structural tests with reference to memory accesses and other logic circuits. Such an approach may not cover paths exercised by actual applications without significant engineering efforts. Therefore, it is widely accepted that processors used in mission critical applications are required to be validated and debugged by emulating their natural instruction set. This methodology of functional testing need not apply to manufacturing tests but has been known to exhibit value add during core frequency based screening of processors.
As the processor speeds increase, the speed on the input/output of the processors is similarly increased. As a result, the typical ATE cannot test the I/O interface of such a fast processor to the limits of the designed performance of the I/O interface. Further, with the existence of widely varying core clock and I/O clock frequencies, processor design can be simplified by allowing the different clock domains to operate asynchronously. However, this further complicates functional testing of vectors because it introduces indeterminism around the clock crossing.
Further, the processors have core cycle speeds of greater than 2 GHz. Unfortunately, the ATE may not be able to input or output data to or from the processors at such high processor core speeds. What is needed is a system and method for accurately transferring data to and from the ATE to test the performance limits of the I/O and the processor core.